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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
FEATURES
* Accepts various HD and SD references including hsync, transport and pixel clock rates * Outputs HD and SD pixel rates * One LVCMOS/LVTTL PLL clock output * Two selectable LVCMOS/LVTTL input clocks * LVCMOS input select lines * VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking * FemtoClock frequency multiplier provides low jitter, high frequency output * FemtoClock range: 560MHz - 700MHz * RMS phase jitter @148.3516484MHz, using a 26.973027MHz crystal (12kHz - 20MHz): 0.81ps (typical) * 3.3V supply voltage * 0C to 70C ambient operating temperature
GENERAL DESCRIPTION
The ICS810001-21 is a member of the HiperClockSTM family of high performance clock HiPerClockSTM solutions from ICS. The ICS810001-21 is a PLL based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation, and to support the complex PLL multiplication ratios needed for video rate conversion. The second stage is a FemtoClock frequency multiplier that provides the low jitter, high frequency video output clock.
IC S
Preset multiplication ratios are selected from internal lookup tables using device input selection pins. The multiplication ratios are optimized to support most common video rates used in professional video system applications. The VCXO requires the use of an external, inexpensive pullable crystal. Two crystal connections are provided (pin selectable) so that both 60 and 59.94 base frame rates can be supported. The VCXO requires external passive loop filter components which are used to set the PLL loop bandwidth and damping characteristics.
OUTPUT RATES SUPPORTED:
Frequency (MHz) 27MHz 26.973027MHz 74.25MHz 74.17582418MHz 148.5MHz 148.3516484MHz 36MHz Application MPEG Transpor t, ITU-R601, CCIR 656
PIN ASSIGNMENT
XTAL_OUT0 XTAL_OUT1 XTAL_SEL XTAL_IN0 XTAL_IN1 GND VDDX VDD
27MHz x 1000/1001 SMPTE 292M/60 SMPTE 292M/59.94 SMPTE 292M/60, 1080P SMPTE 292M/59.94, 1080P SMPTE 259M Level "D"
LF1 LF0 ISET VDD nBP0 GND CLK_SEL CLK1 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
VDD CLK0 MR V0 MF V1 V2 V3
N0 N1 nBP1 OE GND Q VDDO VDDA
ICS810001-21
EXAMPLE FREQUENCY CONVERSIONS:
All nine combinations from / to: 27MHz 74.175MHz 74.25MHz NTSC or PAL hsync to 27MHz NTSC or PAL hsync to 4xFsc
32-Lead VFQFN 5mm x 5mm x 0.95 package body K Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
BLOCK DIAGRAM
XTAL_OUT0 XTAL_IN0 XTAL_OUT1 XTAL_IN1 XTAL_SEL
Loop Filter
ISET
LF0
LF1
0
VCXO Input Pre-Divider (P Value from Table)
Phase Detector
1
CLK0 CLK1 CLK_SEL V3:V0
4
0 1
VCXO
Charge Pump
VCXO Feedback Divider (M Value from Table) VCXO Divider Table
VCXO Jitter Attenuation PLL
10 11
FemtoClock Frequency Multiplier 0= x22 1= x24
01 10 11
Output Divider 00 = 4 01 = 8 10 = 12 11 = 18
00 01 10 11 Q OE
MR MF N1:N0 nBP1:nBP0
2 2
Master Reset
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3 4, 11, 25 5, 22 6, 20, 29 7 8, 9 10, 14, 15, 16 12 Name LF1, LF0 ISET VDD nBP0, nBP1 GND CLK_SEL CLK1, CLK0 V0, V1, V2, V3 MR Type Analog Input/Output Analog Input/Output Power Input Power Input Input Input Pullup Description Loop filter connection node pins. Charge pump current setting pin. Core power supply pins. PLL Bypass control pins. See block diagram.
Power supply ground. Input clock select. When HIGH selects CLK1. When LOW, selects Pulldown CLK0. LVCMOS/LVTTL interface levels. Pulldown Clock inputs. LVCMOS/LVTTL interface levels. Pulldown VCXO PLL divider selection pins. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the output to go low. When logic LOW, the Pulldown internal dividers and the output is enabled. LVCMOS / LVTTL interface levels. FemtoClock multiplication factor select pin. Pulldown LVCMOS/LVTTL interface levels. Analog supply pin. Output power supply pin. VCXO PLL clock output. LVCMOS/LVTTL interface levels. Output enable. When logic LOW, the clock output is in tristate. When logic HIGH, the output is enabled. Pullup LVCMOS/LVTTL interface levels. Pulldown FemtoClock output divide select. LVCMOS/LVTTL interface levels. Cr ystal select. When HIGH, selects XTAL1. When LOW, selects Pulldown XTAL0. LVCMOS/LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output. Cr ystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output. Power supply pin for VCXO charge pump.
Input
13 17 18 19 21 23, 24 26 27, 28 30, 31 32
MF VDDA VDDO Q OE N1, N0 XTAL_SEL XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 VDDX
Input Power Power Output Input Input Input Input Input Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 VDD, VDDA, VDDO = 3.465V TBD 51 51 Maximum Units pF pF k k
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
TABLE 3A. FIRST FREQUENCY TRANSLATION STAGE: VCXO PLL
VCXO PLL Divider Look-Up Table V3:V0 Pins 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 P Value 1000 1001 11000 11011 11000 4004 4004 1000 25 0 253 92 1 1 1 1 1 M Value 1000 1000 4004 4000 4000 4004 4000 1001 91 92 92 600 800 1728 1716 960 Video Clock Application Input (kHz/MHz) 27MHz 27MHz 74.175MHz 74.25MHz 74.25MHz 27MHz 27MHz 26.973MHz 74.175MHz 74.25MHz 27MHz 45kHz (720P/60 hsync) 33.75kHz (1080I/60 hsync) 15.625kHz (PAL hsync) 15.734kHz (NTSC hsync) 28.125kHz (1080I/50 hsync) VCXO (MHz) 27MHz 26.973MHz 27MHz 26.973MHz 27MHz 27MHz 26.973MHz 27MHz 27MHz 27MHz 27MHz 27MHz 27MHz 27MHz 27MHz 27MHz 26.973MHz 44.955kHz (720P/59.94) 33.716kHz (1080I/59.94) 26.973MHz 26.973MHz 26.973MHz 26.973MHz 26.973MHz Alternate Video Clock Application Input (kHz/MHz) 26.973MHz VCXO (MHz) 26.973MHz
TABLE 3B. SECOND FREQUENCY TRANSLATION STAGE: FEMTOCLOCK MULTIPLIER
FemtoClock Look-Up Table MF, N1:N0 Pins 0, 00 0, 01 0, 10 0, 11 1, 00 1, 01 1, 10 1, 11 FB Div 22 22 22 22 24 24 24 24 Out Div 4 8 12 18 4 8 12 18 27MHz 27MHz 54MHz 36MHz Video Clock Application VCXO (MHz) 27MHz 27MHz Q (MHz) 148.5MHz 74.25MHz Alternate Video Clock Application VCXO (MHz) 26.973MHz 26.973MHz Q (MHz) 148.35MHz 74.175MHz
TABLE 3C. BYPASS FUNCTION TABLE
Inputs nBP1 0 0 1 1
810001BK-21
nBP0 0 1 0 1
Operation Bypass Frequency Translator PLL and Output Divider Test Mode: Bypass VCXO Jitter Attenuation PLL and Frequency Translator PLL LC Mode: Bypass VCXO Jitter Attenuation PLL PLL Mode: Active
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TABLE 3D. EXAMPLE FREQUENCY CONFIGURATION TABLE,
CONTINUED ON NEXT PAGE
VCXO PLL P Input Divider VCO_SEL 1 1 1 1 0 0 27 Transpor t 26.973027 148.5 148.3516484 74.25 SMPTE 292M/60 SMPTE 292M/59.94 (1080P) SMPTE 292M/60 (1080P) Transpor t x 1000/1001 74.17582418 SMPTE 292M/59.94 Output Description 1001 1000 1001 1000 1001 1000 1000 27 na na 1000 26.973027 na na 1000 27 22 4 1000 26.973027 22 4 1000 27 22 8 1000 26.973027 22 8 M Feedback Divider XTAL Frequency (MHz) MF Feedback Divider N Output Divider Output Frequency (MHz)
FemtoClock PLL
Configuration Example Number Transpor t Transpor t Transpor t Transpor t Transpor t Transpor t
Input Reference Frequency (MHz)
Reference Clock Description
1
27
2
27
3
27
Integrated Circuit Systems, Inc.
4
27
5
27
6
27
10 292M/60 11000 11000 11000 11000 4004 4004 4004 4004 27 22 8 4000 26.973027 22 8 1 1 4004 27 na na 0 4000 27 na na 0 4004 27 na na 0 4000 27 22 8 1 74.25 27 27 27 74.17582418 74.25 4000 26.973027 22 8 1 74.17582418 11011 4000 26.973027 22 8 1 74.17582418
74.175824
292M/59.94
11000
4004
27
22
8
1
74.25
SMPTE 292M/60 SMPTE 292M/59.94 SMPTE 292M/59.94 SMPTE 292M/60 Transpor t Transpor t Transpor t SMPTE 292M/59.94 HD B
11
74.25
12 292M/60
74.175824
292M/59.94
13
74.25
14 292M/60 Transpor t Transpor t Transpor t
74.175824
292M/59.94
15
74.25
PRELIMINARY
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250 253 253 92 92 27 92 26.973027 22 22 92 27 22 91 27 22 8 8 8 8 1 1 1 1 74.25 74.25 74.17582418 74.25 292M/60 Transpor t 250 253 11011 253 92 4000 92 27 26.973027 26.973027 91 27 na na na na na na na na 0 0 0 0 27 27 26.973027 26.973027 292M/60 292M/60 Transpor t Transpor t Transpor t 4004 92 92 92 92 4004 27 27 27 24 24 24 12 18 18 1 1 1 54 36 36
5
16
27
17
27
18
27
20
74.175824
292M/59.94
SMPTE 292M/60 SMPTE 292M/60 (1080P) SMPTE 292M/59.94 SMPTE 292M/60
21
74.25
22
74.175824
292M/59.94
23
27
30
74.175824
292M/59.94
Transpor t Transpor t Transpor t x 1000/1001 Transpor t x 1000/1001
31
74.25
32
74.25
33
74.175824
292M/59.94
40
27
ITU-R601/656 Oversample 259M Level "D" Oversample 259M Level "D" Oversample
41
27
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FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
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27
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TABLE 3D. EXAMPLE FREQUENCY CONFIGURATION TABLE
VCXO PLL P Input Divider N Output Divider VCO_SEL 0 F1 F1 = 15 to 30MHz Output Clock Description na 92 92 F1 na M Feedback Divider XTAL Frequency (MHz) FC Feedback Divider Output Frequency (MHz) FemtoClock PLL
Configuration Example Number
Input Reference Frequency (MHz)
Reference Clock Description
50
F1
60 1 1 1 na 24 24 12 1 54 12 1 54 na 0 27 Transpor t 1 1 1716 27 1728 27 1716 27 1728 27 na na 0 27 Transpor t 910 14.31818 na na 0 14.31818
0.015625
PAL Hsync
1
1135
17.735
na
na
0
17.735
4x PAL subcarrier (4xFsc) 4x NTSC subcarrier (4xFsc)
Integrated Circuit Systems, Inc.
61 PAL Hsync
0.015734
NTSC Hsync
62
0.015625
63 PAL Hsync
0.015734
NTSC Hsync
64
0.015625
ITU-R601/656 Oversample ITU-R601/656 Oversample
65
0.015734
NTSC Hsync
PRELIMINARY
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FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
REV. A AUGUST 12, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 34.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = VDDX = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO VDDX IDD IDDA IDDO IDDX Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Charge Pump Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Charge Pump Supply Current Test Conditions Minimum 3.135 3.135 3.135 3.135 Typical 3.3 3.3 3.3 3.3 210 10 5 TBD Maximum 3.465 3.465 3.465 3.465 Units V V V V mA mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = VDDX = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage Input High Current CLK0, CLK1, MR, MF, P1:P0, V3:0, N1:0, CLK_SEL, XTAL_SEL OE, nBP0, nBP1 CLK0, CLK1, MR, MF, P1:P0, V3:0, N1:0, CLK_SEL, XTAL_SEL OE, nBP0, nBP1 VOH VOL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 2.6 0.5 Test Conditions Minimum 3.0 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A V V
IIH
IIL
Input Low Current
NOTE 1: Outputs terminated with 50 to VDDO/2.
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ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance VCXO KVCO (KVCXO); NOTE 1 Frequency Pull Range (FP); NOTE 1 7000 100 1 14 Test Conditions Minimum Typical Maximum Fundamental 35 50 7 MHz pF Hz/V ppm mW Units
Drive Level NOTE 1: These parameters are only guaranteed when using an ICS recommended quar tz cr ystal device. Contact ICS regarding quar tz cr ystal device recommendations.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = VDDX = 3.3V5%, TA = 0C TO 70C
Symbol Parameter FOUT tjit(o) t R / tF Output Frequency RMS Phase Jitter, (Random), Configuration 3 of Table 3D; NOTE 1 Output Rise/Fall Time Test Conditions nBP0, nBP1 = 00 nBP1 = 1 148.3516484MHz, (Integration Range: 12kHz - 20MHz) 20% to 80% Minimum 14 31 0.81 450 50 Typical Maximum 35 175 Units MHz MHz ps ps %
odc Output Duty Cycle See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot.
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ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
TYPICAL PHASE NOISE AT 148.3516484MHZ
-10 -20 -30 -40 -50 -60 -70 -80
Fibre Channel Filter 148.3516484MHz
RMS Phase Noise Jitter 12k to 20MHz = 0.81ps (typical)
0
PHASE NOISE
(dBc) HZ
-90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k
Raw Phase Noise Data
Phase Noise Result by adding Fibre Channel Filter to raw data
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
PARAMETER MEASUREMENT INFORMATION
1.65V5%
Phase Noise Plot
VDD, VDDA, VDDO, VDDX
LVCMOS
VEE
Qx
Noise Power
SCOPE
Phase Noise Mask
f1
Offset Frequency
f2
-1.65V5%
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
PHASE JITTER
V
DDO
80% 20% tR
80% 20% tF
Q t PW
t
2
PERIOD
Clock Outputs
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
OUTPUT RISE/FALL TIME
810001BK-21
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL APPLICATION INFORMATION
EXAMPLE LOOP FILTER COMPONENT VALUES
VCXO PLL Divider Selection FB Divider (MValue)
FOR
VARIOUS VCXO DIVIDER SELECTIONS
VCXO PLL Performance VCXO PLL Loop BW (Hz/-3dB) 200 100 20 100 50 20 100 170 125 Damping Factor 1.4 1.4 1.4 1.3 1. 5 1.6 1.6 1.8 1.6 1.5 1.4 1 0.7 1.5 9 8 Loop Filter Example Number 1 2 3 4 5 6 7
Loop Filter Component Selection Rset (k ) 2.2 4.4 4.4 2.2 Iset (A) 500 250 250 500 500 500 250 Rs (k ) 261 261 53.6 499 261 105 23.2 Cs (F) 0.033 0.068 1.5 0.033 0.15 1 1 Cp (pF) 1500 3300 68000 1500 6800 33000 33000
1000, 1001
4000, 4001
2.2 2.2
91, 92 600 800 960 1000, 1000 1726, 1728 4000, 4004 1726, 1728
4.4
4.4
250
261
0.068
2200
105 100 58 27
2.2
500
1000
0.01
47 0
100
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ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
APPLICATION EXAMPLE 1: 27MHZ TO 74.25MHZ
26.973 MHz
27.000 MHz
XTAL_OUT0
ISET
LF0
LF1
RSET = 4.4k (Makes ISET = 250 A)
XTAL_IN0
0
Phase Detector
1
CLK0 = 27 MHz CLK1 = GND CLK_SEL = 0 V3:V0 = 0000
4
0 1
VCXO Input Pre-Divider = 1000
VCXO
Charge Pump
VCXO Feedback Divider = 1000 VCXO Divider Table
VCXO Jitter Attenuation PLL
XTAL_OUT1
XTAL_IN1
XTAL_SEL = 1
VCXO PLL Loop Characteristics with this configuration: - Bandwidth (-3dB) = 100 Hz - Damping Factor = 1.4
Cs = 0.068 F Rs = 261 k Cp = 3300 pf
01 10 11 FemtoClock Frequency Multiplier = x 22 10 11
Output Divider 00 = 4 01 = 8 10 = 12 11 = 18
00 01 10 11 Q = 74.25 MHz OE = 1
MR = 0 MF = 0 N1:N0 = 01 nBP1:nBP0 = 11
2 2
Master Reset
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ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
APPLICATION EXAMPLE 2: 27MHZ TO 74.175MHZ
26.973 MHz 27.000 MHz XTAL_SEL = 0
VCXO PLL Loop Characteristics with this configuration: - Bandwidth (-3dB) = 100 Hz - Damping Factor = 1.4
XTAL_OUT0
ISET
LF0
LF1
RSET = 4.4k (Makes ISET = 250 A)
XTAL_IN0
0
Phase Detector
1
CLK0 = 27 MHz CLK1 = GND CLK_SEL = 0 V3:V0 = 0001
4
0 1
VCXO Input Pre-Divider = 1001
VCXO
Charge Pump
VCXO Feedback Divider = 1000 VCXO Divider Table
VCXO Jitter Attenuation PLL
XTAL_OUT1
Cs = 0.068 F Rs = 261 k Cp = 3300 pf
XTAL_IN1
01 10 11 FemtoClock Frequency Multiplier = x 22 10 11
Output Divider 00 = 4 01 = 8 10 = 12 11 = 18
00 01 10 11 Q = 74.125 MHz OE = 1
MR = 0 MF = 0 N1:N0 = 01 nBP1:nBP0 = 11
2 2
Master Reset
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ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
SETTING THE VCXO PLL LOOP RESPONSE
The VCXO PLL loop response is determined both by fixed device characteristics and by other characterizes set by the user. This includes the values of RS, CS, CP and RSET as shown in the External VCXO PLL Components figure on this page. The VCXO PLL loop bandwidth is approximated by: NBW (VCXO PLL) = RS x ICP x KO 2 x Feedback Divider
DESCRIPTION OF THE PLL STAGES
The ICS843002-21 is a two stage device, a VCXO PLL followed by a low phase noise FemtoClock frequency multiplier. The VCXO uses an external pullable crystal which can be pulled 100ppm by the VCXO PLL circuitry to phase lock it to the input reference frequency. There are two VCXO crystal ports in order to provide VCXO frequency versatility. For HDTV applications, this allows the use of a 26.973027MHz crystal for the generation of 74.175MHz, or a 27.00MHz crystal for the generation of 74.25MHz, for example. The VCXO output frequency can be output directly from the device, or it can be passed to the FemtoClock frequency multiplier which will multiply it up to a higher frequency.
WHERE: RS = Value of resistor RS in loop filter in Ohms ICP = Charge pump current in amps (see table on page 12) KO = VCXO Gain in Hz/V Feedback Divider = 1 to 11011 (as determined by inputs V3:V0) The above equation calculates the "normalized" loop bandwidth (denoted as "NBW") which is approximately equal to the - 3dB bandwidth. NBW does not take into account the effects of damping factor or the second pole imposed by CP. It does, however, provide a useful approximation of filter performance. To prevent jitter on the clock output due to modulation of the VCXO PLL by the phase detector frequency, the following general rule should be observed: NBW (VCXO PLL) (Phase Detector) 20
VCXO PLL LOOP RESPONSE CONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected by the VCXO feedback divider value (bandwidth and damping factor), and by the external loop filter components (bandwidth, damping factor, and 2nd frequency response). A practical range of VCXO PLL bandwidth is from about 1Hz to about 1kHz. The setting of VCXO PLL bandwidth and damping factor is covered later in this document. A PC based PLL bandwidth calculator is also under development. For assistance with loop bandwidth suggestions or value calculation, please contact ICS applications. Table 3A shows frequency translation configuration examples. Note that in the first two V3:V0 selections the VCXO PLL feedback divider is the same value of 1000. This means the VCXO PLL loop response (bandwidth and damping factor) will be the same for all of these settings. The same is true for V3:V0 = 0010 through 0110. This means the device can be configured to translate between 74.175MHz, 74.25MHz, and 27MHz (from any one to another, all nine combinations) and it will maintain the same loop response characteristics. This is also true for V3:V0 = 1000 through 1010. For high VCXO PLL feedback divider values, the phase detector rate, and therefore loop filter charge pulse rate, is greatly reduced. To prevent output clock wander, low leakage capacitors should be used. In addition, when loop bandwidth is low (say below 20Hz), capacitors with low microphonic sensitivity should be used. PPS film type capacitors are one type that perform well in this environment. Below 5Hz, shielding should be considered to prevent excessive phase wander (low frequency phase jitter or clock phase deviation).
(Phase Detector) = Input Frequency / Pre-Divider) The PLL loop damping factor is determined by: RS 2 ICP x CS x KO Feedback Divider
DF = x
WHERE: CS = Value of capacitor CS in loop filter in Farads
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PRELIMINARY
Integrated Circuit Systems, Inc. EXTERNAL VCXO PLL COMPONENTS
In general, the loop damping factor should be 0.7 or greater to ensure output stability. A higher damping factor will create less peaking in the passband. A higher damping factor may also increase lock time and output clock jitter when there is excess digital noise in the system application, due to the reduced ability of the PLL to respond to and therefore compensate for phase noise ingress.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
The best way to set the value of CP is to use the filter response software available from ICS (please refer to the following section). CP should be increased in value until it just starts affecting the passband peak.
NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS
In the loop filter schematic diagram, capacitors are shown between pins 27/30 to ground and between pins 38/31 to ground. These are optional crystal load capacitors which can be used to center tune the external pullable crystal (the crystal frequency can only be lowered by adding capacitance, it cannot be raised). Note that the addition of external load capacitors will decrease the crystal pull range and the Kvco value.
LF1 LF0 CP RS CS ISET
64 1 2 3
27/30
28/31
LOOP FILTER RESPONSE SOFTWARE
Online tools to calculate loop filter response can be found at www.icst.com. Contact your local sales representative if a tool cannot be found for this product.
RSET
The external crystal devices and loop filter components should be kept close to the device. Loop filter and crystal PCB connection traces should be kept short and well separated from each other and from other signal traces. Other signal traces shouldnot run underneath the device, the loop filter or crystal components.
NOTES ON SETTING THE VALUE OF CP
As another general rule, the following relationship should be maintained between components CS and CP in the loop filter: CP = CS 20
CP establishes a second pole in the VCXO PLL loop filter. For higher damping factors (> 1), calculate the value of CP based on a CS value that would be used for a damping factor of 1. This will minimize baseband peaking and loop instability that can lead to output jitter. CP also dampens VCXO PLL input voltage modulation by the charge pump correction pulses. A CP value that is too low will result in increased output phase noise at the phase detector frequency due to this. In extreme cases where input jitter is high, charge pump current is high, and CP is too small, the VCXO PLL input voltage can hit the supply or ground rail resulting in nonlinear loop response.
810001BK-21
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
VCXO CRYSTAL SELECTION
Choosing a crystal with the correct characteristics is one of the most critical steps in using a Voltage Controlled Crystal Oscillator (VCXO). The crystal parameters affect the tuning range and accuracy of a VCXO. Below are the key variables and an example of using the crystal parameters to calculate the tuning range of the VCXO.
VC "Control Voltage"
Oscillator
CV VCXO (Internal)
XTAL
CV
CS1 CL1
CS2 CL2
Optional
FIGURE 1: VCXO OSCILLATOR CIRCUIT EXAMPLE
VC Control voltage used to tune frequency CV Varactor capacitance, varies due to the change in control voltage CL1, CL2 Load tuning capacitance used for fine tuning or centering nominal frequency CS1, CS2 Stray Capacitance caused by pads, vias, and other board parasitics
CRYSTAL PARAMETER EXAMPLES
Symbol fN fT fS CL CO C0/C1 ESR Parameter Nominal Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Aging @ 25C Mode of Operation 3 per year Fundemental 0 12 4 22 0 240 20 1 mW ppm Minimum Typical 19.44 20 20 70 Maximum Units MHz ppm pp m C pF pF
VARACTOR PARAMETERS
Symbol Parameter CV LOW CV HIGH
810001BK-21
Test Condition VC = 0V VC = 3.3V
Typical 15.4 29.6
Unit pF pF
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Low Varactor Capacitance High Varactor Capacitance
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
FORMULAS
CLOW = (CL1 + CS1 + CV_LOW) * (CL2 + CS2 + CV_LOW) (CL1 + CS1 + CV_LOW) + (CL2 + CS2 + CV_LOW) CHIGH = (CL1 + CS1 + CV_HIGH * (CL2 + CS2 + CV_HIGH) (CL1 + CS1 + CV_HIGH) + (CL2 + CS2 + CV_HIGH)
CLow is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance. CLow determines the high frequency component on the TPR (Total Pull Range).
CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance. CHigh determines the low frequency component on the TPR (Total Pull Range).
TPR =
(
1 2 * C0/C1 * (1+CLOW /C0)
-
1 2 * C0/C1 * (1+CHIGH/C0)
* 106
)
the inaccuracy due to aging is 15ppm. Third, though many boards will not require load tuning capacitors (CL1, CL2), it is recommended for long-term consistent performance of the system that two tuning capacitor pads be placed into every design. Typical values for the load tuning capacitors will range from 0 to 4pF. (0 + 4pF + 29.6pF) * (0 + 4pF + 29.6pF) (0 + 4pF + 29.6pF) + (0 + 4pF + 29.6pF)
AbsolutePullRange (APR) = TotalPullRange - (FrequencyTolerance + FrequencyStability + Aging)
EXAMPLE CALCULATIONS
Using the tables and figures above, we can now calculate the TPR and APR of the VCXO using the example crystal parameters. For the numerical example below there were some assumptions made. First, the stray capacitance (CS1, CS2), which is all the excess capacitance due to board parasitic, is 4pF. Second, the expected lifetime of the project is 5 years; hence (0 + 4pF + 15.4pF) * (0 + 4pF + 15.4pF) (0 + 4pF + 15.4pF) + (0 + 4pF + 15.4pF) 1 2 * 220 * (1+9.7pF/4pF) 1 2 * 220 * (1+16.8pF/4pF)
CLOW =
= 9.7pF
CHIGH =
= 16.8pF
TPR =
(
-
)
* 106 = 226.5ppm
TPR = 113.25ppm APR = 113.25ppm - (20ppm + 20ppm + 15ppm) = 58.25ppm
The example above will ensure a total pull range of 113.25 ppm with an APR of 58.25ppm. Many times, board designers may select their own crystal based on their application. If the application requires a tighter APR, a crystal with better pullability
(C0/C1 ratio) can be used. Also, with the equations above, one can vary the frequency tolerance, temperature stability, and aging or shunt capacitance to achieve the required pullability.
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PRELIMINARY
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ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
NOTES ON SETTING CHARGE PUMP CURRENT
The recommended range for the charge pump current is 50A to 300A. Below 50A, loop filter charge leakage, due to PCB or capacitor leakage, can become a problem. This loop filter leakage can cause locking problems, output clock cycle slips, or low frequency phase noise. As can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth and damping factor.
CHARGE PUMP CURRENT, EXAMPLE SETTINGS
RSET 17.6k 8.8k 4.4k 2.2k Charge Pump Current (ICP) 62.5A 125A 250A 500A
1E-3
ICP, Amps
100E-6
10E-6 1k 10k RSET,
VS.
100k
FIGURE 2. CHARGE PUMP CURRENT
VALUE
OF
RSET (EXTERNAL
RESISTOR)
GRAPH
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS810001-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDx, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
810001BK-21
3.3V VDD .01F V DDA .01F 10F 10
FIGURE 3. POWER SUPPLY FILTERING
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN
JA vs. 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W
TRANSISTOR COUNT
The transistor count for ICS810001-21 is: 9365
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
FOR
PACKAGE OUTLINE
AND
DIMENSIONS - K SUFFIX
32 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL N A A1 A3 b ND NE D D2 E E2 e L 0.30 1.25 1.25 5.00 BASIC 2.25 5.00 BASIC 2.25 0.50 BASIC 0.40 0.50 3.25 3.25 0.18 0.80 0 MINIMUM NOMINAL 32 --0.25 Ref. 0.25 0.30 8 8 1.00 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
810001BK-21
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REV. A AUGUST 12, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS810001-21
FEMTOCLOCKSTM DUAL VCXO VIDEO PLL
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS810001BK-21 ICS810001BK-21T Marking ICS10001B21 ICS10001B21 Package 32 Lead VFQFN 32 Lead VFQFN Shipping Packaging tray 2500 tape & reel Temperature 0C to 70C 0C to 70C
The aforementioned trademarks, HiPerClockSTM and FEMTOCLOCKSTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 810001BK-21
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